1. Field of the Invention
The present invention relates to operational amplifiers in general and more particularly to apparatus and methods which negate the offset voltages associated with said amplifiers.
2. Prior Art
Operational amplifiers may be used for a wide variety of purposes, such as those in which high gain amplification is required. A conventional high gain operational amplifier consists of at least an input and an output stage. A signal provided at the input stage is amplified and outputted at the output stage.
A significant disadvantage that plagues all operational amplifiers is voltage offset. This offset is present even in the absence of an input signal. As set forth in an article entitled "MOS Operational Amplifier Design," a tutorial overview, by Paul R. Gray et al, IEEE Journal Solid State Circuits, Vol. SC-17, pp. 969-982, Dec. 1982, the offset voltage of an op amp is consisted of two components, random offset and systematic offset. Random offset results from mismatches due to process variations in supposedly identical pairs of devices. In MOSFET op amps random offset is primarily due to threshold voltage mismatch. Threshold voltage mismatch is a function of process cleanliness and uniformity. Similarly, capacitance mismatch between supposedly identical silicon gate MOS capacitors is also a function of process variations. Systematic offset is caused by mismatches between cascaded stages of an op. amp. and is present even with perfect device matching.
For precision applications, it is desirable to cancel all offset voltages. The prior art describes several techniques for cancelling op. amp. offset voltages. Some of these techniques are set forth in the following articles: H. Schmidt, "Electronic Analog/Digital Conversions," pages 387-389 New York, Van NostrandReinhold, 1970, R. Poujors, B. Boylac, D. Barbier and J. M. Ittel, "Low Level MOS Transistor Amplifier Using Storage Techniques," ISSCC Dig. Tech. Papers, Feb. 1973 and U.S. Pat. No. 4,439,693. Primarily, these methods used switched capacitor circuits.
Usually the offset voltage is stored during one clock cycle and subtracted during another clock cycle. Even though this technique works well for its intended purpose, its main drawback is that it requires clocks and sampling techniques to cancel the offset. As a result, the switched capacitor approach does not allow the op amp to amplify signals approaching the frequency limit of the technology. In addition, the switched capacitor technique is a sampled one and does not allow for continuous amplification. Also switched capacitor circuits consume large amounts of area, and the clock signals can introduce noise into the signal.
As can be seen from the above description, these techniques are dynamic. Dynamic techniques can be costly and undesirable for some applications. Thus, there is a need for a static method to eliminate offset voltages in CMOS operational amplifiers.
Another prior art method which is used to negate offset voltage is the so-called "common centroid geometries." This method is particularly suited for matching silicon-gate MOS capacitors and is described by Paul R. Gray, James L. McCreary, "ALL-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part 1," IEEE Solid State Circuits, Vol. SC-10, pp. 371-379, Dec. 1975. However, published data (see O. H. Shade, Jr. "BIMOS Micropower Integrated Circuits," IEEE Solid-State Circuits, Vol. SC-13, pp. 791-7998, Dec. 1978 and O. H. Shade, Jr. and E. J. Kramner, "A Low-Voltage BIMOS Op Amp," IEEE SolidState Circuits, Vol. SC-16, pp. 661-668, Dec. 1981) seems to indicate that large-geometry common-centroid matched transistors are also capable of significantly improving transistor mismatch distributions. The large geometries effectively eliminate the second order effects of process variations. Hence, process variations can be approximated as first order gradients within a physically close area.
Even though the common centroid geometries work well with two-terminal capacitors, using it with three-terminal transistors can require intricate physical designs. Large common centroid geometries consume large amounts of area. In addition, the common centroid method does not compensate for systematic offset. Finally, prior art techniques that compensate for systematic offsets require sacrificing low noise and best frequency response under capacitive loading.